The invention generally relates to electronic protection devices, and more particularly to electrostatic discharge (ESD) protection devices.
Integrated circuits are susceptible to a variety of reliability problems. One of these issues is the possible vulnerability to ESD events. ESD occurs when a charged object, e.g., a piece of equipment used to install integrated circuits into a printed circuit board, is brought into close proximity to a pin of an integrated circuit that is at a different potential compared to the charged object. The discharge consists, typically, of current levels exceeding an ampere during a time period less than 200 nanoseconds. The magnitude of the peak current and the waveshape of the discharge depend on the effective resistance, capacitance and inductance of the system and the amount of charge present before the discharge. The result of ESD on unprotected integrated circuits is often destruction characterized by melting and/or explosion of part of the circuit. It is common practice for the designer to include extra components in an integrated circuit that are intended to provide protection against ESD damage by providing paths for the ESD events that bypass the components used for the normal circuit functions and are not destroyed by the ESD events.
In BiCMOS integrated circuits, a frequently used circuit configuration is a differential pair 10 of bipolar transistors, as shown in FIG. 1. When this configuration is used as an input with the bases of the transistors connected to external bonding pads, it is very difficult to protect these transistors from ESD events.
A typical ESD protection scheme is shown in FIG. 2. If pad A is stressed positive with respect to pad B, one of the likely paths for the ESD current is through a resistor R1, the forward biased base-emitter junction BE-1, the reverse biased base-emitter junction BE-2, and a resistor R2. In high frequency integrated circuits, transistors Q1 and Q2 are small in area, significantly limiting the ability of the base-emitter junction to carry current in the forward direction before the internal power dissipation is sufficient to cause damage. The base-emitter junction is very weak in the reverse direction, with a typical breakdown voltage of 4 V or less. Resistors R1 and R2 are often low-valued resistors to improve performance. The result of this configuration is that it is very difficult to protect the differential pair against the effects of ESD events.
The ESD protection scheme shown in FIG. 2 is required to limit the voltage between points C and D to a safe value during a typical ESD event, where the discharge current may exceed 2 A. For high forward currents, the internal series resistance of the diode results in a larger forward drop (typically 2 to 3 V) than the typical low current diode drop (0.7 V). The preferred current path would be through diode D1, a power supply clamp 12, and diode D2. If it is assumed that the voltage drop across power supply clamp 12 is 5 V, and the voltage across each of the two diodes in forward bias under the ESD event is 3 V, then 11 V appears from pad A to pad B. Also, if it is assumed that the current through the reverse biased BE-2 is limited to 10 mA with a voltage drop of 4 V and that the voltage drop across the forward biased BE-1 is 0.6 V at 10 mA, then the voltage drop across resistor R1 plus resistor R2 must be 6.4 V at 10 mA. The result is that R1 and R2, which are equal, must be at least 320 kxcexa9 to protect the device. For high performance, it may be necessary to limit R1 and R2 to less than 100xcexa9 each. Note that it may be necessary to limit the current through the reverse biased base-emitter junctions to 1 mA or less for very small devices. An alternative is to increase the physical size of the transistors, which degrades the performance, to improve ESD protection.
An alternative approach is to divert the current from the input pads A and B directly. One such approach is shown in FIG. 3, where anti-parallel diodes, D5 and D6, are connected between pads A and B. This approach limits the voltage across the differential pair to one high current diode drop (approximately 3 V), if the same assumptions as in the above for FIG. 2 are used. Note that the other diodes are also necessary to provide protection for ESD stresses from the pads to the power supply and ground. The major difficulty with this approach is that the input signal is also diverted by the diode pair D5 and D6, limiting the input swing to approximately 0.6 V in either polarity. If the input swing is larger than this voltage, the anti-parallel diodes D5 and D6 are no longer a valid solution for ESD protection.
Therefore, there is a need for an effective ESD protection scheme that allows a larger swing of an input voltage.
The invention provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on the parasitic bipolar npn transistor triggering into snap-back as in the grounded gate n-MOS transistor that is commonly used for ESD protection in CMOS integrated circuits.
According to the present invention, an ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals. The circuit comprises a switching element (such as an NMOS transistor) having first and second terminals and a control terminal; a first resistive element, coupled between the first and control terminals of the switching element; and a second resistive element, coupled between the second and control terminals of the switching element; wherein the first and second terminals of the switching element are for connecting, respectively, to input terminals of the different pair.
According to one embodiment of the invention, the first and second resistive elements in the protection circuit are two resistors. The resistance values of the two resistors are preferably equal.
According to another embodiment of the invention, each of the first and second resistive elements in the protection circuit includes a parallel circuit. Each parallel circuit includes a pair of anti-parallel diodes.
According to a further embodiment of the invention, each parallel circuit in the protection circuit further includes two resistors each connected in series with one of the diodes of the parallel circuit. The resistance values of the two resistors in each parallel circuit are preferably equal.